1. Field of the Invention
The present invention relates to automated design tools for integrated circuit, charge trapping memory devices.
2. Description of Related Art
The design of SONOS type memory devices, which are based on dielectric charge trapping structures, involves complex tradeoffs among parameters that are not well understood. Thus, suitable tools for simulating such devices have not been developed.
For example, while the erase speed of a SONOS type device could be significantly improved by using a high-κ blocking layer, where κ is the dielectric constant, and a metal gate with a high work function (C. H. Lee et al., IEDM Tech. Dig., pp. 613-616, 2003), program saturation becomes a problem. So to counter the program saturation problem, a programming high voltage is necessary to achieve either a fast program speed or a large memory window in such devices. The loss of injected electrons through the blocking layer is highly suspected as a cause of lower program saturation levels, as described in Furnemont et al., NVSMW, pp 94-95, 2007, and J. Fu et al., IEDM Tech. Dig., pp. 79-82, 2007. Therefore, reducing the overall thickness of the charge trapping layer, or a band-engineered process, becomes necessary, causing other tradeoffs in performance or cost of manufacturing. To optimize these tuning concepts, a comprehensive understanding of device programming (PGM), erasing and read disturb behaviors is necessary. Although many transport theories have been proposed in Paul et al., IEDM Tech. Dig., December, 2006, Furnemont et al., NVSMW, pp 96-97, 2007, and possibly others, a consistent model illustrating programming, erasing and read disturb behaviors in charge trapping memory cells is not available.
Therefore, it is desirable to provide a consistent programming model and a simulator based on such model for use in an integrated circuit design tool.